FPCWAY

Currently, Flexible Printed Circuit (FPC) technology has been widely applied. With the development of PCB manufacturing technology and material technology, a new type of ultra-thin FPC (with an interlayer thickness of less than 1 mil) has begun to be used. As the interlayer thickness decreases, challenges in FPC layout design arise. Currently, there are three common methods for FPC layout design: (1) single-layer without a reference plane; (2) mesh reference plane; (3) solid copper reference plane. Due to the parallel plate capacitance effect, ultra-thin FPCs will exhibit larger parasitic capacitances, which directly lead to degraded signal quality and even failure to transmit signals correctly. The edge rate of signals is severely weakened, leading to timing and other signal integrity issues. In contrast, traditional FPCs with larger interlayer spacing (about 2 mils) do not have this problem as seriously.

Furthermore, among the current FPC layout design methods, extensive testing and simulation have proven that both ultra-thin FPCs with no reference plane and those with conventional mesh copper reference planes have poor EMC performance and weak anti-interference capabilities.

In summary, there are two main issues in the current ultra-thin FPC layout design: (1) The wiring on ultra-thin FPCs with a solid copper reference plane will generate larger parasitic capacitances, affecting the signal quality of the wiring, reducing the signal edge rate, and impacting the normal transmission of signals; (2) FPCs with no reference layer or a mesh copper reference plane have normal signal rates but poor EMC performance, making them prone to self-radiation and susceptible to external interference. Since the design method without a reference layer cannot improve EMC performance, this article does not discuss this approach, focusing only on the two design methods with mesh copper and solid copper reference planes.